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19-3982; Rev 0; 10/07
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
General Description
The MAX8655 synchronous-PWM buck regulator operates from a 4.5V to 25V input and generates an output voltage adjustable from 0.7V to 5.5V at loads up to 25A. Integrated power MOSFETs provide a small footprint, ease of layout, and reduced EMI. Removing the board trace inductances ensures the highest efficiency at high frequency. The MAX8655 uses peak current-mode control architecture with an adjustable (200kHz to 1MHz), constantswitching frequency, which is externally synchronizable. The MAX8655's adjustable current limit uses the inductor's DC resistance to improve efficiency or an external sense resistor for higher accuracy. Foldback type current limit is available to reduce the power dissipation under severe-overload or short-circuit conditions. A reference input is provided for use with a high-accuracy external reference or for DDR and tracking applications. Monotonic startup provides safe starting into a prebiased output, where traditional step-down regulators discharge the output capacitor during soft-start, creating a negative voltage at the output and possibly damaging the load. A 180 out-of-phase synchronization output is available for synchronizing with another MAX8655. An enable input is provided for on/off control and to facilitate output sequencing. Output-voltage sensing for programmable overvoltage protection is provided and is independent of the feedback network to further enhance the output overvoltage protection. Overall, the MAX8655 provides enough flexibility for the experienced user, as well as simplicity and ease of use for non-power-supply engineers. 25A Output Current Integrated Power MOSFETs Operates from 4.5V to 25V Supply 1% FB Voltage Accuracy Over Temperature Adjustable Output Voltage Down to 0.7V Adjustable Switching Frequency and External Synchronization from 200kHz to 1MHz Multiphase Operation with Accurate Current Sharing 180 Phase-Shifted Synchronization Adjustable Overcurrent Limit Adjustable Slope Compensation Selectable Current-Limit Mode: Latch-Off or Automatic Recovery Monotonic Output Voltage Rise at Startup into Prebias Output Output Sources and Sinks Current for DDR Applications Enable Input Power-OK (POK) Output Adjustable Soft-Start Independently Adjustable Overvoltage Protection
Features
MAX8655
Typical Operating Circuit
Applications
Point-of-Load Power Supplies Telecom Power Networking Nonisolated DC-DC Power Modules Servers and Workstations Notebook Computers IBA Power Supplies
FB COMP OVP SCOMP ILIM2 POWER-OK OUTPUT POK ILIM1 CSCS+ PVIN SYNC OUTPUT OFF ENABLE INPUT ON EN VLGND OUTPUT 0.7V TO 12V UP TO 25A SYNCO IN VL LX GND SS MODE
FSYNC INPUT
FSYNC
MAX8655
Ordering Information
PART MAX8655ETN+ TEMP RANGE -40C to +85C PINPACKAGE 56 TQFN-EP* (8mm x 8mm) PKG CODE T5688M-4
VL
BST
LXB INPUT 7V TO 28V PVIN PGND REFIN AVL
AVL
+Denotes a lead-free package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
ABSOLUTE MAXIMUM RATINGS
PVIN, IN, EN to GND ..............................................-0.3V to +30V BST to LXB ............................................................-0.3V to +7.5V LX, LXB to GND............ (-2.5V for < 50ns transient) -1V to +30V ILIM2, ILIM1, SYNCO, FSYNC, OVP, SCOMP to GND .....................................-0.3V to (VAVL + 0.3V) VL to PGND ...........................................................-0.3V to +7.5V AVL, FB, POK, COMP, SS, MODE, REFIN to GND ..-0.3V to +6V CS+, CS- to GND ....................................................-0.3V to +6V PGND to GND to VLGND ......................................-0.3V to +0.3V Operating Junction Temperature Range .......... -40C to +125C Junction Temperature ......................................................+150C JC (thermal resistance from junction to exposed pad) (Note 1) ...............................3.5C/W JT (thermal resistance from junction to the top) ............3.9C/W ILX (RMS) .................................................................................27A Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VBST - VLX = 6.5V, TA = -40C to +85C, circuit of Figure 4, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER PVIN Operating Voltage Range IN Operating Voltage Range IN Quiescent Supply Current Shutdown Supply Current PVIN Shutdown Supply Current AVL Undervoltage-Lockout Threshold Output-Voltage Adjust Range VL Regulation Voltage AVL Regulation Voltage AVL Output Current SOFT-START SS Shutdown Resistance SS Soft-Start Current REFIN INPUT REFIN Dual ModeTM Threshold REFIN Input Bias Current REFIN Input Voltage Range VREFIN = 0.7V to 1.5V VAVL 1.0V -250 0 VAVL +250 1.5 V nA V From SS to GND, VEN = 0V VREF = 0.625V 18 20 23 100 28 A VL = IN for VIN < 7V VFB = 0.75V, no switching EN = GND, VIN 28V IIN + IVL + IAVL, EN = GND, VAVL = VVL = VIN = 5V VPVIN = VLX = VBST VAVL rising, 3% typical hysteresis Minimum output voltage is limited by minimum duty cycle and external components 7V < VIN < 28V 5.5V < VVL < 7V, 1mA < ILOAD < 10mA 3.90 0.7 6.0 4.900 10 6.5 4.975 1 4.15 4.40 5.5 7.0 5.050 CONDITIONS MIN 3 4.5 2 TYP MAX 25 25.0 3 10 32 UNITS V V mA A A V V V V mA
Dual Mode is a trademark of Maxim Integrated Products, Inc.
2
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VBST - VLX = 6.5V, TA = -40C to +85C, circuit of Figure 4, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER ERROR AMPLIFIER REFIN = AVL FB Regulation Voltage Transconductance COMP Shutdown Resistance FB Input Leakage Current FB Input Common-Mode Range CURRENT-SENSE AMPLIFIER Voltage Gain CURRENT LIMIT Peak Current-Limit Threshold (VCS+ - VCS-) Negative Current Limit CS+, CS- Input Bias Current CS+, CS- Input Common-Mode Range SLOPE COMPENSATION VSCOMP = 2.5V Slope Compensation at Maximum Duty Cycle VSCOMP = 1.25V SCOMP = AVL SCOMP = GND SCOMP High Threshold SCOMP Low Threshold SCOMP Adjustment Range SCOMP Input Leakage Current VSCOMP = 1.25V to 2.5V 0.5 1.25 5 2.50 200 TA = 0C to +85C TA = -40C to +85C 231.25 113.77 231.25 113.77 110.70 250.00 123.00 250.00 123.00 123.00 268.75 132.23 268.75 132.23 132.23 VAVL 0.5 V V V nA mV RILIM1 = 24k ILIM1 = AVL % of valley current limit VCS+ = VCS- = 0 or 5.5V 27.2 60 -90 -25 0 32 80 -120 36.8 92 -150 +25 5.5 mV % A V VCS+ - VCS- = 30mV VOUT = 0 to 5.5V Part to part variation at TA = +85C -4 12 +4 V/V % From COMP to GND, VEN = 0V VFB = 0.7V -0.1 VREFIN = 0.7V to 1.5V 0.693 VREFIN 0.00375 70 0.7 VREFIN 110 20 5 0.707 VREFIN + 0.00375 160 100 50 +1.5 V S nA V CONDITIONS MIN TYP MAX UNITS
MAX8655
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, VBST - VLX = 6.5V, TA = -40C to +85C, circuit of Figure 4, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER OSCILLATOR Switching Frequency Minimum Off-Time Minimum On-Time FSYNC Synchronization Range FSYNC Input High Pulse Width FSYNC Input Low Pulse Width FSYNC Rise/Fall Time SYNCO Phase Shift SYNCO Output Low Level SYNCO Output High Level FSYNC Input Low FSYNC Input High THERMAL PROTECTION Thermal Shutdown Thermal-Shutdown Hysteresis POK POK Threshold POK Output Voltage, Low POK Leakage Current, High OVP OVP Threshold Voltage OVP, Leakage Current, High MODE CONTROL MODE Logic-Level Low MODE Logic-Level High MODE Input Current SHUTDOWN CONTROL EN Logic-Level Low EN Logic-Level High EN Input Current 4.5V VAVL 5.5V 4.5V VAVL 5.5V VEN = 0V VEN = 28V 2 -1 1.5 +1 6.0 0.45 V V A 4.5V VAVL 5.5V 4.5V VAVL 5.5V VMODE = 0 to VAVL 1.8 -1 +1 0.4 V V A REFIN = AVL VREFIN = 0.7V to 1.5V VOVP = 0.8V 770 110 800 115 840 120 500 mV % nA REFIN = AVL, VFB rising, typical hysteresis is 3% VREFIN = 0.75V to 1.5V, VFB rising, typical hysteresis is 3% VFB = 0.6V, IPOK = 2mA VPOK = 5.5V 629 88.7 650 91.7 25 671 94.7 200 1 mV % mV A Rising temperature +160 15 C C 2.5 ISYNCO = 5mA ISYNCO = -5mA VAVL - 1V 0.4 180 0.4 RFSYNC = 21.0k RFSYNC = 143k Measured at LX Measured at LX 160 100 100 100 800 160 1000 200 235 75 100 1200 1200 240 kHz ns ns kHz ns ns ns Degrees V V V V CONDITIONS MIN TYP MAX UNITS
Note 2: Specifications are 100% production tested at TA = +85C. Limits over the operating temperature range are guaranteed by design.
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
LOAD REGULATION (CIRCUIT OF FIGURE 4)
MAX8655 toc01
LINE REGULATION (CIRCUIT OF FIGURE 4)
MAX8655 toc02
FB VOLTAGE vs. EXPOSED PAD TEMPERATURE (CIRCUIT OF FIGURE 4)
7.5A LOAD 0.715 0.710 FB VOLTAGE (V) 0.705 0.700 0.695 0.690 0.685 0.680
MAX8655 toc03
3.34 3.33 OUTPUT VOLTAGE (V) 3.32 3.31 3.30 3.29 3.28 3.27 3.26 0 5 10 15 LOAD CURRENT (A)
VIN = 12V
3.34 12A LOAD 3.33 OUTPUT VOLTAGE (V) 3.32 3.31 3.30 3.29 3.28 3.27 3.26
0.720
20
25
5
10 15 INPUT VOLTAGE (V)
20
-40
0 40 80 EXPOSED PAD TEMPERATURE (C)
120
OSCILLATOR FREQUENCY vs. INPUT VOLTAGE (CIRCUIT OF FIGURE 4)
MAX8655 toc04
STEP-LOAD RESPONSE (CIRCUIT OF FIGURE 3)
MAX8655 toc05
400 390 OSCILLATOR FREQUENCY (kHz) 380 370 360 350 340 330 320 310 300 8 13 18 23 INPUT VOLTAGE (V) TA = +85C TA = +25C RFSYNC = 76.8k TA = -40C
VOUT = 1.2V VOUT 50mV/div (AC-COUPLED) 0A
IOUT 5A/div
28
40s/div
POWER-UP WAVEFORMS (CIRCUIT OF FIGURE 4)
MAX8655 toc06
POWER-DOWN WAVEFORMS (CIRCUIT OF FIGURE 4)
MAX8655 toc07
ENABLE WAVEFORMS (CIRCUIT OF FIGURE 4)
MAX8655 toc08
VPOK 10V/div 5V/div VIN 10V/div
VPOK 5V/div VEN
1V/div VIN VOUT 5A/div ILX ILX 10A/div ILX 200s/div 2ms/div VPOK VOUT 2V/div VOUT 5V/div
5V/div
2V/div
10A/div
2ms/div
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
FSYNC AND SYNCO (CIRCUIT OF FIGURE 4)
MAX8655 toc09
DUAL-PHASE SWITCHING (CIRCUIT OF FIGURE 5)
MAX8655 toc10
VFSYNC
5V/div
VLX (SLAVE)
5V/div
VLX
5V/div
VLX (MASTER) VSYNCO (MASTER) 1s/div
5V/div
VSYNCO INTERNAL 350kHz SYNCHRONIZED TO OPERATION EXTERNAL 500kHz CLOCK 1s/div
5V/div
5V/div
SHORT CIRCUIT AND RECOVERY
MAX8655 toc11
OVERVOLTAGE PROTECTION (CIRCUIT OF FIGURE 3)
MAX8655 toc12
VIN VOUT
500mV/div (AC-COUPLED) 1V/div
VOUT
2V/div
VLX 5V/div
IIN 1A/div
40s/div
1ms/div
CLOSED-LOOP BODE PLOT (CIRCUIT OF FIGURE 3)
50 40 30 20 GAIN (dB) 10 0 -10 -20 -30 -40 500 1k 2k 4k 10k 20k 40k 100k 200k400k FREQUENCY (Hz) 0 5 GAIN PHASE
MAX8655toc13
SAFE OPERATING AREA
144 PHASE MARGIN (DEGREES) 108 72 36 0 25 OUTPUT CURRENT (A) 20 15 10 5
MAX8655 toc14
180
30
10
15 20 INPUT VOLTAGE (V)
25
30
6
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAXIMUM OUTPUT CURRENT vs. EXPOSED PAD TEMPERATURE (CIRCUIT OF FIGURE 4)
MAX8655 toc15
EFFICIENCY vs. INPUT VOLTAGE (CIRCUIT OF FIGURE 4)
MAX8655 toc16
EFFICIENCY vs. OUTPUT VOLTAGE (CIRCUIT OF FIGURE 4)
90 80 70 EFFICIENCY (%) 60 50 40 30 20
MAX8655 toc17
30 25 OUTPUT CURRENT (A) 20 15 10 5 0 -40 -20 0 20 40 60 80 100 120 EXPOSED PAD TEMPERATURE (C)
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 5 8 11 14 INPUT VOLTAGE (V) 17 VO = 3.3V 10A LOAD
100
10 0 20 1.0 1.5
12V INPUT 10A LOAD 2.0 2.5 3.0 OUTPUT VOLTAGE (V) 3.5
EFFICIENCY vs. LOAD CURRENT 12V INPUT, 3.3V OUTPUT (CIRCUIT OF FIGURE 4)
MAX8655 toc18
EFFICIENCY vs. FREQUENCY 12.0V INPUT 3.3V OUTPUT (CIRCUIT OF FIGURE 4)
MAX8655 toc19
RVALLEY vs. VALLEY CURRENT LIMIT
180 160 140 RVALLEY (k) 120 100 80 60 40
MAX8655 toc20
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 1 10 LOAD CURRENT (A)
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 10A LOAD 200 300 400 500 600 FREQUENCY (kHz) 700
200
20 0 800 0 5 10 15 20 VALLEY CURRENT LIMIT (A) 25
100
BOTTOM LAYER PCB TEMPERATURE vs. OUTPUT CURRENT
MAX8655 toc21
OUTPUT-CURRENT CAPABILITY vs. AMBIENT TEMPERATURE
300 LFM OUTPUT-CURRENT CAPABILITY (A) 25 20 15 10 NO AIRFLOW 5 0 100 LFM
MAX8655 toc22
120 VIN = 12V, VCC = 1.2V BOTTOM PCB TEMPERATURE (C) 100 80 60 40 20 0 0 5 10 15 IOUT (A) 20
30
25
-40 -25 -10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (C)
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Pin Description
PIN 1-5, 51-56 6, 16-21 7-15 22 23, 28, 39, 48 NAME PVIN LX PGND VLGND GND FUNCTION Power-Input Supply. PVIN connects to the drain of the internal high-side MOSFET. Connect inputdecoupling capacitors as close as possible between PVIN and PGND. External Inductor Connection. Connect to the external power inductor. Leave pin 6 unconnected for best routing. Power Ground Connection from Source of Internal Low-Side MOSFET. Connect input-decoupling capacitors as close as possible between PVIN and PGND. Return for Low-Side MOSFET Gate-Driver Current Analog Ground. Connect all pins to the analog ground plane, and connect the analog and power ground planes together at the negative terminal of the output capacitor. Low-current signals return to GND. Pin 28 must be connected externally to GND-EP, the analog ground plane. Internal 6.5V Linear-Regulator Output. Connect a 2.2F to 10F ceramic capacitor from VL to VLGND. For VIN < 7V, connect VL directly to IN. VL supplies power for the internal gate drivers. VL is the input to the AVL internal linear regulator. Input Supply Voltage. IN is the input to the VL linear regulator. Connect VL to IN for VIN < 7V. Decouple to PGND with a 0.22F ceramic capacitor. Enable. Apply logic-high to EN to enable the output, or logic-low to place the regulator in low-power shutdown mode. Connect EN to IN for always-on operation. Internal 5V Linear-Regulator Output. AVL powers the MAX8655's internal circuits. Connect a 1F ceramic capacitor from AVL to GND. No Connection. Not internally connected. Positive Differential Current-Sense Input Negative Differential Current-Sense Input Analog Programmable Current-Limit Input for Inductor Current. Connect a resistor from ILIM1 to GND to set the overcurrent threshold. ILIM1 sources 10A through the resistor, and the voltage at ILIM1 is attenuated 7.5:1 to set the final current limit. For example, a 60k resistor results in 600mV at ILIM1. This results in a current-limit threshold (VCS+ - VCS-) of 80mV. The ILIM1 resistor range is 24k to 60k. Connect ILIM1 to AVL to set the default threshold of 80mV. Output-Voltage Sensing for Overvoltage Protection. Connect OVP to the center of a resistor-divider connected between the output of the regulator and GND to set the FB independent output overvoltage trip point. Connect OVP to FB if this independence is not desired. The OVP threshold is 1.15 times the nominal feedback regulation voltage. Feedback Input. Connect FB to the center of a resistor voltage-divider connected between the output and GND to set the output voltage. FB regulates to 0.7V or VREFIN. Loop Compensation. Connect COMP to an external RC network to compensate the loop. COMP is internally pulled to GND through 20 during shutdown. Soft-Start. Connect a 0.01F to 1F ceramic capacitor from SS to GND. This capacitor sets the softstart period during startup. See the Startup and Soft-Start section for more details. SS is internally pulled to GND through 20 during shutdown. External Reference Input. Connect REFIN to AVL to use the internal 0.7V reference for the feedback threshold.
24
VL
25 26 27 29, 30, 42, 49 31 32
IN EN AVL N.C. CS+ CS-
33
ILIM1
34
OVP
35 36
FB COMP
37
SS
38
REFIN
8
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Pin Description (continued)
PIN 40 NAME ILIM2 FUNCTION Programmable Current-Limit Input. Connect a resistor from ILIM2 to GND to set the valley current limit. See the Setting the Current Limit section. Programmable Slope-Compensation Input. Internal slope-compensation voltage rate is the voltage at SCOMP times 0.1 divided by the oscillator period (T). Connect SCOMP to AVL or GND to set to the default of 250mV/T or 125mV/T, respectively. Open-Drain Power-OK Output. POK goes high impedance when the output voltage rises above 91% of the nominal regulation voltage. POK pulls low during shutdown or when the output drops below 88% of the nominal regulation voltage. Frequency Set and Synchronization Input. Connect a resistor from FSYNC to GND to set the switching frequency, or drive with a clock signal to synchronize between 160kHz and 1.2MHz. See the Switching Frequency and Synchronization section. Current-Limit Operating Mode Selection. Connect MODE to AVL for latch-off current limit or connect MODE to GND for automatic recovery current limit. Synchronization Output. Provides a clock output for synchronizing another MAX8655 with 180 out-of-phase operation. Boost Capacitor Connection. Connect a 0.22F ceramic capacitor from BST to LXB. LX Boost Capacitor Connection. Connect a 0.22F ceramic capacitor between LXB and BST. Exposed Pad. Connect to GND externally. See the Pin Configuration. Exposed Pad. Internally connected to PVIN. See the Pin Configuration. Exposed Pad. Internally connected to LX. See the Pin Configuration.
MAX8655
41
SCOMP
43
POK
44
FSYNC
45 46 47 50 -- -- --
MODE SYNCO BST LXB GND-EP PVIN-EP LX-EP
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
IN
MAX8655
6.5V LDO REGULATOR UVLO
BST PVIN LEVEL SHIFT LX SHOOT-THROUGH PROTECTION VL
EN VL
THERMAL SHDN 5V AVL LDO VOLTAGE REFERENCE REF SELECT LOGIC
AVL
VREF
PWM CONTROL LOGIC PGND VLGND SYNCO OVP 1.15V REF OSCILLATOR FSYNC
REFIN SS ERROR AMPLIFIER GM FB COMP OVP CS+ 12 LEVEL SHIFT X1 CS10A VL
SOFT-START CIRCUITRY
COMP CLAMP SLOPE COMP PWM COMPARATOR
SCOMP
CURRENT-SENSE AMPLIFIER
VSUM CURRENT-LIMIT CONTROL LOGIC
MODE
CURRENT-LIMIT COMPARATOR ILIM2
POK ILIM1 GND /7.5 0.9V REF FB
Figure 1. Functional Diagram
10
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Detailed Description
DC-DC Converter Control Architecture
The MAX8655 step-down regulator uses a PWM, peak current-mode control scheme. An internal transconductance amplifier establishes an integrated error voltage. The heart of the PWM controller is a PWM comparator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus an adjustable slope-compensation ramp, which is summed with the current signal to ensure stability. At each rising edge of the internal clock, the internal highside MOSFET turns on until the PWM comparator trips or the maximum duty cycle is reached. During this ontime, current ramps up through the inductor, storing energy in the output inductor while sourcing current to the output. The current-mode feedback system regulates the peak inductor current as a function of the output-voltage error signal. The circuit acts as a switch-mode transconductance amplifier and pushes the output LC filter pole normally found in a voltagemode PWM to a higher frequency. Figure 1 is the functional diagram. During the second half of the cycle, the internal highside MOSFET turns off and the internal low-side MOSFET turns on. The output inductor releases the stored energy as the current ramps down, providing current to the load. The output capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the Current-Limit Circuit section), the high-side MOSFET is turned off immediately and the low-side MOSFET is turned on and remains on to let the inductor current ramp down until the next clock cycle. Under severe-overload or short-circuit conditions, the valley foldback current limit is enabled to reduce power dissipation of external components. The MAX8655 operates in a forced-PWM mode. As a result, the regulator maintains a constant switching frequency, regardless of load, to allow for easier filtering of the switching noise.
Internal Linear Regulators
The MAX8655 contains two internal LDO regulators. The AVL regulator provides 5V for the IC's internal circuitry, and the VL regulator provides 6.5V for the MOSFET gate drivers. Connect a 2.2F ceramic capacitor from VL to VLGND, and connect a 1F ceramic capacitor from AVL to GND. The AVL regulator input is internally connected to the VL regulator output. For 5V input applications, connect VL directly to IN and connect a 10 resistor from VL to AVL.
MAX8655
Undervoltage Lockout
When VAVL drops below 4.03V, the MAX8655 assumes that the supply voltage is too low to make valid decisions, so the undervoltage-lockout (UVLO) circuitry inhibits switching and turns off both internal power MOSFETs. When VAVL rises above 4.15V, the regulator enters the startup sequence and then resumes normal operation.
Startup and Soft-Start
The internal soft-start circuitry gradually ramps up the reference voltage to control the rate of rise of the output voltage and reduce input surge currents during startup. The soft-start period is determined by the value of the capacitor from SS to GND. The soft-start time is approximately (30.4ms/F) x CSS. The MAX8655 also features monotonic output-voltage rise; therefore, both power MOSFETs are kept off if the voltage at FB is higher than the voltage at SS. This allows the MAX8655 to start up into a prebiased output without pulling the output voltage down. Before the MAX8655 begins the soft-start and powerup sequence, the following conditions must be met: * VAVL exceeds the 4.15V UVLO threshold. * EN is at logic-high. * The thermal limit is not exceeded.
Enable
The MAX8655 features a low-power shutdown mode. A logic-low at EN shuts down the regulator. During shutdown, the output is high impedance. Shutdown reduces the IN current to less than 10A. A logic-high at EN enables the regulator.
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Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
The valley current is sensed across the on-resistance of the low-side MOSFET. The valley current limit trips when the sensed current exceeds the valley current limit. Set the minimum valley current limit when the output voltage is at its nominal regulated value, higher than the maximum peak current-limit setting. With this method, the current-limit point accuracy is controlled by the peak current limit and is not interfered with by the wide variation of the MOSFET's on-resistance. See the Setting the Current Limit section for how to set these limits. The MAX8655 can be configured for either an adjustable valley current-limit threshold with adjustable foldback ratio or a fixed valley current limit that latches the regulator off. To use foldback current limit with autorecovery, connect MODE to GND. When the latch-off mode is used, connect MODE to AVL and set the current-limit threshold with one resistor from ILIM2 to GND. Cycle EN or input power to reset the current-limit latch. The peak current limit is used to sense the inductor current, and is more accurate than the valley current limit because it does not depend upon the on-resistance of the low-side MOSFET. The peak current can be measured across the resistance of the inductor for the highest efficiency, or alternatively, a current-sense resistor can be used for more accurate current sensing. A resistor connected from ILIM1 to GND sets the peak current-limit threshold. For more information on the current limit, see the Setting the Current Limit section.
MAX8655
VL BST
MAX8655
LXB
Figure 2. High-Side Gate Boost Circuit
High-Side Gate-Drive Supply (BST)
A flying capacitor boost circuit (Figure 2) generates the gate-drive voltage for the internal high-side n-channel MOSFET. The capacitor between BST and LXB is charged from VL to 6.5V minus the diode forward-voltage drop while the low-side MOSFET is on. When the low-side MOSFET is switched off, the stored voltage of the capacitor is stacked above LXB to provide the necessary turn-on voltage (VGS) for the high-side MOSFET. An internal switch between BST and the internal highside MOSFET's gate closes to turn the MOSFET on.
Current-Sense Amplifier
The current-sense circuit amplifies the differential current-sense voltage (VCS+ - VCS-). This amplified current-sense signal and the internal-slope-compensation signal are summed (VSUM) together and fed into the PWM comparator's inverting input. The PWM comparator shuts off the high-side MOSFET when V SUM exceeds the integrated feedback voltage (VCOMP). The differential current sense is also used to provide peak inductor current limiting. This current limit is more accurate than the valley current limit, which is measured across the internal low-side MOSFET.
Switching Frequency and Synchronization
The MAX8655 has an adjustable internal oscillator that can be set to any frequency from 200kHz to 1MHz. To set the switching frequency, connect a resistor from FSYNC to GND. The MAX8655 can also be synchronized to an external clock by connecting the clock signal to FSYNC. A synchronization output (SYNCO) is provided to synchronize a second MAX8655 180 out-of-phase with the first by connecting SYNCO of the first MAX8655 to FSYNC of the second. When the first MAX8655 is synchronized to an external clock, the external clock is inverted to generate SYNCO. Therefore, to get 180 out-of-phase operation with an external clock, the clock input to the first MAX8655 should have a 50% duty cycle. Figure 3 is the single-phase, 600kHz switching, 10.8V to 13.2V input and 1.2V/20A output. Figure 4 shows single-phase, 350kHz switching, 6V to 20V input, and 3.3V/20A output.
Current-Limit Circuit
The MAX8655 uses both foldback and peak current limiting. The valley foldback current limit is used to reduce power dissipation of external components--mainly the inductor, internal power MOSFETs, and the upstream power source, when the output is severely overloaded or short circuited and when POK is low. Thus, the circuit can withstand short-circuit conditions continuously without causing overheating of any component. The peak constant current limit sets the current-limit point more accurately since it does not have to suffer the wide variation of the low-side power MOSFET's on-resistance due to tolerance and temperature.
12
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
R12 80.6k R3 2.87k C8 0.47F C12 470pF R7 40.2k R2 357 C10 100pF
AVL
C13 R10 0.022F 51.1k AVL
R5 4.02k
R9 56.2k
ILIM2
GND
SS
FB
CS-
OVP
REFIN
ILIM1
CS+
N.C.
SCOMP
POWER-OK OUTPUT POK FSYNC INPUT FOR INTERNAL OSCILLATOR OPERATION ONLY SYNC OUTPUT R8 41.2k
COMP
N.C. GND AVL EN IN VL GND C18 2.2F PVIN C16 0.22F C9 0.47F
R13 100k
FSYNC MODE
C14 1F ENABLE INPUT OFF ON
SYNCO D1 VL BST GND N.C. LXB INPUT 11.8V TO 13.2V PVIN PVIN C1-C3 3 x 10F CERAMIC PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN LX
C15 0.22F
MAX8655
VLGND LX LX LX LX LX LX PGND
R1 681
OUTPUT 1.2V UP TO 20A
L1 0.56H 1.8m C6-C20 4 x 100F CERAMIC
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Figure 3. Single-Phase, 600kHz Switching, 10.8V to 13.2V Input, and 1.2V/20A Output
REFIN
The MAX8655 has a reference input (REFIN). When an external reference up to 1.5V is connected to REFIN, the feedback regulation voltage is equal to the voltage applied to REFIN. Connect REFIN to AVL to use the internal 0.7V reference.
PGND
Power-Good Signal (POK)
POK is an open-drain output on the MAX8655 that monitors the output voltage. When the output is above 92% of its nominal regulation voltage, POK is high impedance. When the output drops below 89% of its nominal regulation voltage, POK is internally pulled low. POK is also internally pulled low when the MAX8655 is shut down or in a fault condition.
Overvoltage Protection
The MAX8655 provides output overvoltage protection (OVP). The OVP threshold is set independent of the output regulation voltage with a resistor voltage-divider. When the voltage at OVP exceeds the OVP threshold, the regulator stops switching and latches on the lowside power MOSFET. Cycle EN or the power applied to AVL to clear the latch.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8655. When the junction temperature exceeds +160C, an internal thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the IC on again after the junction temperature cools by 15C, resulting in a pulsed output during continuous thermal-overload conditions.
13
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
R3 11.5k R4 11.5k C8 0.22F R12 10k AVL R14 13k C13 0.022F R11 140k AVL C12 560pF R7 243k R5 3.09k R6 3.09k R9 71.5k R2 3.57k C10 100pF
SS
FB
OVP
GND
REFIN
ILIM2
ILIM1
CS+
CS-
N.C.
POWER-OK OUTPUT POK FSYNC INPUT FOR INTERNAL OSCILLATOR OPERATION ONLY SYNC OUTPUT SYNCO D1 VL BST GND N.C. LXB INPUT 6V TO 20V PVIN PVIN C1-C5 5 x 10F CERAMIC PVIN PVIN PVIN PVIN PVIN R8 76.8k AVL FSYNC MODE
SCOMP
COMP
N.C. GND AVL EN IN VL GND C18 2.2F PVIN C16 0.22F C9 0.22F
R13 100k
C14 1F ENABLE INPUT OFF ON
C15 0.22F
MAX8655
VLGND LX LX LX LX LX LX PGND
R1 1.74k OUTPUT 3.3V UP TO 20A L1 1H 1.6m C6-C19 3 x 220F 15 ESR
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Figure 4. Single-Phase, 350kHz Switching, 6V to 20V Input, and 3.3V/20A Output
Design Procedure
Setting the Output Voltage
To set the output voltage for the MAX8655, connect FB to the center of an external resistor-divider from the output to GND (R3 and R5 of Figure 5). Select R5 between 5k and 24k, and then calculate R3 with the following equation: V R3 = R5 x OUT - 1 VFB where VFB = 0.7V or VREFIN . R3 and R5 should be placed as close as possible to the IC.
LX
PGND
PVIN
PVIN
PVIN
PVIN
LX
MAX8655
FB
R3
R5
Figure 5. Setting the Output Voltage with a Resistor VoltageDivider
14
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Setting the Output Overvoltage Protection
To set the overvoltage threshold voltage for the MAX8655, connect OVP to the center of an external resistor-divider connected between the output and GND (R4 and R6 of Figure 3). Select R6 between 5k and 24k, then calculate R4 with the following equation: V R4 = R6 x OUT - 1 VOVP where VOVP = 1.15 x VFB.
Setting the Switching Frequency
To set the switching frequency, connect a resistor from FSYNC to GND. Calculate the resistor value in k from the following equation: RFSYNC = 30600 - 9.914 fS
MAX8655
where fS is the desired switching frequency in kHz.
Setting the Slope Compensation Inductor Selection
For most applications where the duty cycle is less than 40%, connect SCOMP to GND to set the internal slope compensation to the default of 125mV/T, where T is the oscillator period (T = 1 / fS). For a slope compensation of 250mV/T, connect SCOMP to AVL. For applications with a duty cycle greater than 40%, set the SCOMP voltage with a resistor voltage-divider from AVL to GND (R11 and R12 in Figure 6). First, use the following equation to find the SCOMP voltage: VSCOMP = 120 x RL x (VO - 0.182 x VIN _ MIN ) fS x L
There are several parameters that must be examined when determining which inductor is to be used. Input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of the inductor current ripple to the maximum DC load current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. A good compromise between size and efficiency is an LIR of 0.3. Once all the parameters are chosen, the inductor value is determined as follows: VOUT x (VIN - VOUT ) L= VIN x fS x ILOAD(MAX) x LIR where fS is the switching frequency. Choose a standard-value inductor close to the calculated value. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. This is especially true if the inductance is increased without also increasing the physical size of the inductor. Find a low-loss inductor having the lowest possible DC resistance that fits the allotted dimensions. The chosen inductor's saturation current rating must exceed the peak inductor current determined as: IPEAK = ILOAD(MAX) + LIR x ILOAD(MAX) 2
where RL is the DC resistance of the inductor, VIN_MIN is the minimum operating input voltage, and fS is the switching frequency. Next, select a value for R11, typically 10k, and solve for R12 as follows: R12 =
(5V - VSCOMP ) x R11
VSCOMP
This sets the internal slope-compensation voltage rate to VSCOMP / (10 x T).
AVL R12
MAX8655
SCOMP
R11
Figure 6. Resistor-Divider for Setting the Slope Compensation
______________________________________________________________________________________
15
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Setting the Current Limit
Valley Current Limit The MAX8655 has an adjustable valley current limit, configurable for foldback with automatic recovery, or constant-current limit with latch-up. To set the constantcurrent limit for the latch-up mode, connect a single resistor RILIM2 from ILIM2 to GND. For latch-up currentlimit mode, set RILIM2 equal to RVALLEY obtained from the RVALLEY vs. Valley Current Limit graph in the Typical Operating Characteristics section for the required valley current IVALLEY. IVALLEY is the value of the inductor valley current at maximum load (ILOAD(MAX) - 1/2 IP-P) To set the current limit for foldback mode, connect a resistor from ILIM2 to the output (RFOBK), and another resistor from ILIM2 to GND (RILIM2). See Figure 7. The values of RFOBK and RILIM2 are calculated as follows. First, select the percentage of foldback (PFB). This percentage corresponds to the current limit when VOUT equals zero divided by the current limit when V OUT equals its nominal voltage. A typical value of PFB is in the 15% to 40% range. A lower value of P FB yields lower short-circuit current. The following equations are used to calculate RFOBK and RILIM2: RFOBK = RILIM 2 = PFB x VOUT IILIM2 x (1- PFB ) RILIM1 = 7.5 x VTH 10A
This allows a maximum DC output current of: V I ILIM = TH - P-P RL 2 where RL is the DC resistance of the inductor. To ensure maximum output current, use the minimum value of VTH from each setting, and the maximum RL values at the highest expected operating temperature. The DC resistance of the inductor's copper wire has a +0.38%/C temperature coefficient. An RC circuit is connected across the inductor (see Figure 8). The RC time constant is set to be 1.1 to 1.2 times the inductor (L/RL) time constant. Pick the value of C9 in the 0.1F to 0.47F range, and then calculate R1 from: R1 = 1.2L / (RL x C9) Add a resistor (R2 in Figure 8) to the CS- connection to minimize input offset error. Calculate the value of R2 as follows: * When VOUT 2.4V: RILIM1 x 10A 20A + x R1 32k R2 = 20A * When VOUT < 2.4V: R2 = 15A x R1 RILIM1 x 10A 15A + 32k
IILIM 2 x RVALLEY x RFOBK VOUT + (IILIM 2 x (RFOBK - RVALLEY ))
where IILIM2 is 5A. If the resulting value of RILIM2 is negative, increase PFB. Peak Current Limit The peak current-limit threshold (VTH) is set by a resistor connected from ILIM1 to GND (RILIM1). VTH corresponds to the peak voltage across the sensing element (inductor or current-sense resistor). RILIM1 is calculated as follows:
LX
OUT
L1 LX R1
VOUT
MAX8655
ILIM2
RFOBK
MAX8655
CS+ C10
C9
R2
C11
RILIM2
CS-
Figure 7. ILIM2 Resistor Connections 16
Figure 8. Current Sense Using the Inductor's DC Resistance
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Capacitor C11 is connected in parallel with R2 and is equal in value with C9. Add a 100pF (C10) capacitor across the CS+ and CSinputs close to the IC.
MAX8655
V -V V IP-P = IN OUT x OUT fS x L VIN These equations are suitable for initial capacitor selection, but final values should be chosen based on a prototype or evaluation circuit. As a general rule, a smaller current ripple results in less output-voltage ripple. Since the inductor ripple current is a factor of the inductor value and input voltage, the output-voltage ripple decreases with larger inductance, and increases with higher input voltages. The MAX8655 is designed to work with polymer, tantalum, aluminum electrolytic, or ceramic output capacitors. The aluminum electrolytic capacitor is the least expensive; however, it has higher ESR. To compensate for this, use a ceramic capacitor in parallel to reduce the switching ripple and noise. Ceramic capacitors are recommended for high-frequency (500kHz to 1MHz) designs. For reliable and safe operation, ensure that the capacitor's voltage and ripple-current ratings exceed the calculated values. The response to a load transient depends on the selected output capacitors. During a load transient, the output voltage instantly changes by ESR x I LOAD. Before the regulator can respond, the output voltage deviates further, depending on the inductor and outputcapacitor values. After a short time (see the Typical Operating Characteristics section), the regulator responds by regulating the output voltage back to its nominal state. The regulator response time depends on its closed-loop bandwidth. With a higher bandwidth, the response time is faster, thus preventing the output voltage from further deviation from its regulating value.
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitors must meet the ripple-current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD VOUT x (VIN - VOUT ) VIN
I RMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) = ILOAD / 2. Ceramic capacitors are recommended due to the low ESR and ESL at high frequency with relatively low cost. Choose a capacitor that exhibits less than 10C temperature rise at the maximum operating RMS current for optimum long-term reliability. Ceramic capacitors with an X5R or better temperature characteristic are recommended.
Output Capacitor
The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), the equivalent series inductance (ESL), and the voltage-rating requirements. These parameters affect the overall stability, output-voltage ripple, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor's ESR, and ESL caused by the current into and out of the capacitor. The maximum output-voltage ripple is estimated as follows: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL) The output-voltage ripple as a consequence of the ESR, ESL, and output capacitance is: VRIPPLE(ESR) = IP-P x ESR VRIPPLE(ESL) = VRIPPLE(C) = VIN x ESL L + ESL IP-P 8 x COUT x fS
Compensation Design
The MAX8655 uses an internal transconductance error amplifier whose output compensates the control loop. The external inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. Additionally, the compensation resistor and capacitors are selected to optimize control-loop stability. The component values, shown in Figures 3 and 4, yield stable operation over the given range of input-to-output voltages. The regulator uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. The voltage drop across the DC resistance of the inductor or the alternate series current-sense resistor is used to measure the inductor current. Current-mode control eliminates the double pole in the feedback loop caused by the
where IP-P is the peak-to-peak inductor current.
______________________________________________________________________________________
17
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
inductor and output capacitor resulting in a smaller phase shift and requiring a less elaborate error-amplifier compensation than voltage-mode control. A simple series RC and CC is all that is needed to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering. For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output-capacitor loop, add another compensation capacitor from COMP to GND to cancel this ESR zero. See Figure 9. The basic regulator loop is modeled as a power modulator, an output feedback divider, and an error amplifier. The power modulator has DC gain GMOD(dc), set by gmc x RLOAD, with a pole and zero pair set by RLOAD, the output capacitor (COUT), and its equivalent series resistance (ESR). Below are equations that define the power modulator: RLOAD GMOD(dc) = gmc x RLOAD x KS x (1 - D) - 0.5 1 + L x fS where RLOAD = VOUT / IOUT(MAX), fS is the switching frequency, L is the output inductance, gmc = 1 / (AVCS x RL), where AVCS is the gain of the current-sense amplifier (12 typ), RL is the DC resistance of the inductor, the duty cycle D = VOUT / VIN. KS is a slope compensation factor calculated from the following equation:
MAX8655
fzMOD =
1 2 x COUT x ESR
[(
)
]
When COUT comprises "n" identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR = ESR(EACH) / n. Note that the capacitor zero for a parallel combination of like capacitors is the same as for an individual capacitor. Figure 10 is the simplified gain plot for the fzMOD > fC case. The feedback voltage-divider has a gain of GFB = VFB / VOUT, where VFB is equal to 0.7V. The transconductance error amplifier has a DC gain, GEA(DC) = gmEA x RO, where gmEA is the error-amplifier transconductance, which is equal to 110S, and RO is the output resistance of the error amplifier, which is 30M. A dominant pole (fpdEA) is set by the compensation capacitor (CC), the amplifier output resistance (RO), and the compensation resistor (RC); a zero (fzEA) is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole (fpEA) set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency (fC). Thus: fpdEA = 1 2 x CC x (RO + RC ) 1 2 x CC x RC 1 2 x CF x RC
VSCOMP x L x fS KS = 1 + 120 x (VIN - VO ) x RL When SCOMP is connected to GND, use VSCOMP = 1.25V; when SCOMP is connected to AVL, use VSCOMP = 2.5V. Find the pole and zero frequencies created by the power modulator as follows: 1 fpMOD = + 2 x RLOAD x COUT 1 x [KS x (1 - D) - 0.5] 2 x L x fS x COUT
GAIN (dB) POWER MODULATOR
fzEA =
fpEA =
CLOSED LOOP
COMP CF
fc 0dB fpMOD FB DIVIDER
ERROR AMPLIFIER
MAX8655
RC CC
FREQUENCY
fzMOD
Figure 9. Compensation Components 18
Figure 10. Simplified Gain Plot for the fzMOD > fC Case
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
The crossover frequency, fC, should be much higher than the power-modulator pole fPMOD. Also, fC should be less than or equal to 1/5 the switching frequency. Select a value for fC in the range: f fpMOD << fC S 5 At the crossover frequency, the total loop gain must equal 1, and is expressed as: GEA(fc) x GMOD(fc) x VFB =1 VOUT
CLOSED LOOP GAIN (dB) POWER MODULATOR ERROR AMPLIFIER
The error-amplifier gain at fC is: f GEA(fc) = gmEA x RC x zMOD fC Figure 11 is the simplified gain plot for the fzMOD < fC case.
MAX8655
For the case where fzMOD is greater than fC: GEA(fc) = gmEA x RC GMOD(fc) = GMOD(dc) x Then RC can be calculated as: VOUT RC = gmEA x VFB x GMOD(fc) where gmEA = 110S. The error-amplifier compensation zero formed by RC and CC should be set at the modulator pole fPMOD. Calculate the value of CC as follows: CC = 1 2 x fp
MOD
fpMOD fC
0dB fpMOD FB DIVIDER fzMOD fc FREQUENCY
Figure 11. Simplified Gain Plot for the fzMOD < fC Case
RC is calculated as: V fC RC = OUT x VFB gmEA x GMOD(fc) x fzMOD where gmEA = 110S. CC is calculated from: CC = CF is calculated from: CF = 1 2 x RC x fzMOD 1 2 x fp
MOD
x RC
If fzMOD is less than 5 x fC, add a second capacitor CF from COMP to GND. The value of CF is: CF = 1 2 x RC x fzMOD
x RC
As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. For the case where fzMOD is less than fC: The power modulator gain at fC is: GMOD(fc) = GMOD(dc) x fpMOD fzMOD
The current-mode control model on which the above design procedure is based requires an additional highfrequency term, GS(s), to account for the effect of sampling the peak inductor current. The term G S (s) produces additional phase lag at crossover and should be modeled to estimate the phase margin obtainable by the selected compensation components. As a final step, it is useful to plot the dB gain and phase of the following loop-gain transfer function and check the
______________________________________________________________________________________
19
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
obtained phase margin. A phase margin of at least 45 is recommended: GLOOP (s) = gmc x RLOAD RLOAD x (KS x (1 - D)) - 0.5 1 + L x fS (1 + s / 2 x fzMOD ) x (1 + s / 2 x fpMOD ) x
RLOAD = RLOAD 1 + L x fs x KS x (1 - D) - 0.5 0.06 = 2.53 46.29 x 0.06 x [1.18(1 - 0.1) - 0.5] 1+ (0.56 x10 -6 )(600000) GMOD(dc) = gmc x
[(
)
]
[
]
fpMOD =
1 + 2 x RLOAD x COUT x 0.9 1 x [KS x (1 - D) - 0.5] = 2 x L x fS x COUT x 0.8 1 + 2(400x10 -6 )(0.06) x 0.9 1 (1.18(1 - 0.1) - 0.5) = 8.18kHz 2(0.56 x10 -6 )(600000)(400x10 -6 ) x 0.8
(1 + s / 2 x fzEA ) x (1 + s / 2 x fpEA ) x (1 + s / 2 x fpdEA ) gmEA x Ro x VFB GS (s) VO GS (s) = 1 s s2 1 + + .Qc.fS ( .f )2 S
f fpMOD << fC S 5 8.18kHz << fC 120kHz, select fC = 60kHz.
fzMOD = 1 1 = = 884.2kHz 2 x 0.9 x COUT x ESR 2 x 0.9 x (400 x 10 -6 ) x 0.0005
where the sampling effect quality factor: QC = 1 [.(KS.(1 - D) - 0.5)]
Since fzMOD > fC:
GMOD( fc) = GMOD(dc) x fpMOD fc = 2.53 x 8118 = 0.345 60000
, Below is a numerical example to calculate RC and CC values of the typical operating circuit of Figure 3: AVCS = 12 L = 0.56H RL = 1.8m fS = 600kHz gmc = 1 / (AVCS x RL) = 1 / (12 x 0.0018) = 46.29S VOUT = 1.2V IOUT(MAX) = 20A RLOAD = VOUT / IOUT(MAX) = 1.2 / 20 = 0.06 COUT = 4 x 100F = 400F ESR = 2m/4 = 0.5m D = VOUT / VIN = 1.2/12 = 0.1: KS = 1 + VSCOMP x L x fS 120 x (VIN - VO ) x RL
V 1 RC = OUT x VFB gmEA x GMOD( fc) 1.2 1 = x -6 0.7 (110 x10 )(0.307) RC = 44.7k Select the nearest standard value: RC = 40.2k:
CC = 1 2 x fp
MOD
x RC
=
1 2 x 8181 x (40.2 x103 )
= 483.9pF
Select the nearest standard value: CC = 470pF:
CF = 1 1 = = 5pF 2 x RC x fzMOD 2 x (40.2 x 103 ) x (884.2 x103 )
1.25(0.56 x10 -6 )(600000) = 1+ 120(12 - 1.2)(0.0018) = 1.18
R7 = RC = 40.2k C12 = CC = 470pF C11 = CF = 5pF (not used)
20
______________________________________________________________________________________
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low losses and clean, stable operation. Refer to the MAX8655 Evaluation Kit for an example layout. If it is necessary to deviate from this layout, follow the procedure below. Follow these guidelines for good PCB layout: 1) Place IC decoupling capacitors as close as possible to the IC pins. Separate the power and analog ground planes. Place the input ceramic decoupling capacitor directly across and as close as possible to PVIN and PGND. This is to help contain the high switching current within this small loop. 2) For output current greater than 10A, a four-layer PCB is recommended. Pour an analog ground plane in the second layer underneath the IC to minimize noise coupling. 3) Connect input, output, and VL capacitors to the power ground plane; connect all other capacitors to the signal ground plane. Connect analog and power ground planes at the output capacitor. 4) Place the inductor current-sense resistor and capacitor as close as possible to the inductor. Make a Kelvin connection to minimize the effect of PCB trace resistance. Place the input bias balance resistor (R2 in Figure 8) near CS-. Run two closely parallel traces from across capacitor C9 to CS+ and the input bias balance resistor R2. 5) Connect the exposed pad sections to the corresponding IC pins and allow sufficient copper area to help cooling the device. 6) Place the feedback and compensation components as close as possible to the IC pins. Connect the feedback resistor-divider from FB to VOUT as close as possible to the farthest output capacitor.
MAX8655
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
21
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Pin Configuration
SCOMP COMP REFIN ILIM2 ILIM1
TOP VIEW
N.C.
GND
OVP
N.C.
42 41 40 39 38 37 36 35 34 33 32 31 30 29 POK 43 FSYNC 44 MODE 45 SYNCO 46 BST 47 GND 48 N.C. 49 LXB 50 PVIN 51 PVIN 52 PVIN 53 PVIN 54 PVIN 55 PVIN 56 1 PVIN + 2 PVIN 3 PVIN 4 PVIN 5 PVIN 6 LX 7 PGND 8 PGND 9 PGND 10 11 12 13 14 PGND PGND PGND PGND PGND PVIN-EP LX-EP GND-EP 28 GND 27 AVL 26 EN 25 IN 24 VL
N.C. 23 GND 22 VLGND 21 LX 20 LX 19 LX 18 LX 17 LX 16 LX 15 PGND
MAX8655ETN
THIN QFN (8mm x 8mm)
22
______________________________________________________________________________________
CS+
CS-
SS
FB
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX8655
______________________________________________________________________________________
56L THIN QFN.EPS
23
Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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